A modulator popular in current market usually has an adjustable function of variable symbol rate. However, a symbol rate and a clock frequency has a direct relationship, thus, in present, a variable symbol rate is usually implemented through a clock adjustable chip outputting a variable clock signal, so that the symbol rate can be adjusted.
All the chips with clock adjustable function of the main stream of the current market are chips adopting a direct digital frequency synthesis (DDFS, DDS for short) technology. The so-called DDS is a new technology of frequency synthesis that synthesizes the required wave directly from the concept of phase. At present, major chip manufacturers one after another offer high-performance, multi-functional DDS chips produced with newest complementary metal-oxide-semiconductor (CMOS) technology, such as the AD9910, AD9912 chips of the Analog Devices Cooperation, which can be used for outputting a variable clock signal.
FIG. 1 shows a circuit schematic diagram of a DDS chip, in which the DDS generates a frequency and phase controlled sine wave through a digitally controlled oscillator. The DDS chip generally includes a frequency accumulator 110, a phase accumulator 120, an amplitude/phase converter circuit 130, a digital-analog converter (DAC) 140 and a low-pass filter (LPF) 150, wherein:
The frequency accumulator 110 is used for operating an accumulating calculation of input signal (fin labeled in FIG. 1), and generating a frequency control word X (also called phase step value).
The phase accumulator 120 is further cascaded by an N-bit full adder 121 and a N-bit accumulator register 122, from FIG. 1, the phase accumulator 120 is a typical feedback circuit used for operating an accumulating calculation of the binary frequency control word X that represents frequency, and generating an accumulated phase data Y, the accumulated phase data Y is output after being locked by the N-bit accumulator register 122.
The amplitude/phase converter circuit 130 is essentially a waveform memory, which is used for making a table lookup based on the accumulated phase data Y generated by the phase accumulator 120 and transmitting the obtained data to DAC 140, and the data is further transmitted to the LPF 150 through the DAC 40.
The detailed work process of above-mentioned DDS chip is described as follows.
The DDS chip is connected to a reference clock fz, when receiving a clock pulse, the N-bit full adder 121 adds the frequency control word X and the accumulated phase data Y generated in the prior cycle of the current clock cycle fed back by the N-bit accumulator register 122 together, and transmits the added result to the input end of the N-bit accumulator register 122.
In one aspect, the new accumulated phase data Y generated from the current clock cycle is fed back to the input end of the N-bit full adder 121 through the N-bit accumulator register 122, so that the adder can continue to add the frequency control word X with the function of the pulse of the later cycle of the current cycle; in another aspect, the accumulated phase data Y is transmitted to the amplitude/phase converter circuit 130 as a sampling address value.
Based on the sampling address value, the amplitude/phase converter circuit 130 looks up the waveform data corresponding to the address value, and outputs a corresponding waveform data.
It should to be pointed out is that, the waveform data output by the amplitude/phase converter circuit 130 is a digital data, and the digital data is converted into an analog signal through the DAC 140, a sine wave with output frequency fs is obtained after the stray wave and the harmonic wave being filtered by the LPF 150, and the output frequency fs is determined by fz, X and N, that is, fs=X*fz/2N, wherein X<2N−1.
For example, suppose that the reference clock fz is 70 MHz, the phase accumulator 120 is a 16-bit accumulator (that is, N=16), binary frequency control word X is 4096, then, 4096×70/216=4.375 MHz.
Due to the reference clock fz generally is fixed, thus, in theory, the output with any frequency can be generated by setting the bit (that is, the value of N) and the value of the frequency control word X.
However, the clock adjustable chip can output a variable clock signal, but also has some evident defects.
First, the clock adjustable chip has high cost and high price, for example, the chips such as AD9910, AD9912, the price of the single chip usually is much higher the other elements in the modulator apparatus.
In addition, in use, the adjustable range of the output symbol rate is larger, and the generality is better, but the adjustable range of the output symbol rate is larger, the frequency range of the system clock of the modulator is correspondingly larger. For example, if a system requires an output symbol rate of 2 Mbps˜9 Mbps, the relationship of the system clock frequency and the output symbol rate is 20:1, and the corresponding adjustable range of the system clock is 40 MHz˜180 MHz. In actual signal system, when the work frequency range of the system clock chip is large, a harmonic wave and a stray wave difficult to be removed may be generated inside the chip in work, thus, it make a great impact on the work performance of the whole system.